VHDL implementation of pipeline calculating Y=A*B+C

I have VHDL code, which implements Y=A*B+C pipeline in three stages, as illustrated below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pipeline is
   Port (A : in std_logic_vector (15 downto 0);
      B : in std_logic_vector (15 downto 0);
      C : in std_logic_vector (15 downto 0);
      Y : out std_logic_vector (32 downto 0);
      CLK : in std_logic;
      RESET : in std_logic);
end pipeline;

architecture Behavioral3 of pipeline is
   signal OUT_A, OUT_B, OUT_C : std_logic_vector (15 downto 0);
   signal OUT_MUL_2, OUT_C_2 : std_logic_vector (31 downto 0);

   begin
      Stage1: process(CLK, RESET)
         begin
            if RESET ='0' then
               OUT_A <= x"0000";
               OUT_B <= x"0000";
               OUT_C <= x"0000";
            elsif CLK ='1' and CLK'event then
               OUT_A <= A;
               OUT_B <= B;
               OUT_C <= C;
            end if;
       end process;

       Stage2: process(CLK, RESET)
          begin
             if RESET = '0' then
                OUT_MUL_2 <= x"00000000";
                OUT_C_2 <= x"00000000";
             elsif CLK ='1' and CLK'event then
                OUT_MUL_2 <= OUT_A * OUT_B ;
                OUT_C_2 <= x"0000" & OUT_C ;
             end if;
       end process;

       Stage3: process(CLK, RESET)
          begin
             if RESET ='0' then
                Y <= (others => ‘0’);
             elsif CLK ='1' and CLK'event then
                Y <= (‘0’ & OUT_MUL_2) + (‘0’ & OUT_C_2);
             end if;
       end process;
end Behavioral3;

Question: Why in the process "Stage3" the code is :

Y <= (‘0’ & OUT_MUL_2) + (‘0’ & OUT_C_2);

rather than :

Y <= OUT_MUL_2 + OUT_C_2;

Wouldn't the implementation as written yield an OUT signal Y of always 0 (low), because anything&0 is always 0 and 0+0 is again 0 ?