I have a couple of clarifications on the statements below(source - https://mechanical-sympathy.blogspot.in/2011/09/single-writer-principle.html):
'x86/x64 have a memory model, whereby load/store memory operations have preserved order, thus memory barriers are not required if you adhere strictly to the single writer principle.
On x86/x64 "loads can be re-ordered with older stores" according to the memory model so memory barriers are required when multiple threads mutate the same data across cores. '
Does this mean that :
1. Within a single core , load/store memory operations are always in order?
So a single writer thread (and multiple reader threads ) on a single core system would not need to 'synchronize' to resolve visibility issues?
2. For multiple cores, loads can be re-ordered with stores initiated from other cores ?
So a single writer thread ( and multiple reader threads running on other cores ) would not need to 'synchronize' to resolve visibility issues (as there wont be any stores)?
So,if we strictly maintain a single writer - we can actually do away with the practice of using 'synchronized' on both reads and writes in primitive locks. We can actually do away with 'synchronized' completely?