I know that different architectures may provide different ways to let developer detect whether the cpu is running in ISR now, e.g. reading a register.
But I do found that in some BSP code, they use a global variable,it is called g_in_isr, as a flag to indicating whether cpu running in ISR. When an interrupt occurred the interrupt handler will perform g_in_isr++ operation on entery and g_in_isr-- on exit.
I am wondering if this way is safe on the architectures which allows nested interrupt. In most architectures, g_in_isr++ or g_in_isr-- is not atomic operation (am I right?), what if an high priority interrupt comes while an existing interrupt handler is doing g_in_isr++ operation? Doesn't it cause problems?
Update (2016-03-27)
Yeah, I know it is architecture dependent, but I want to know the general case. Let us assume that g_in_isr++ is not atomic, it is indeed not atomic on most architecture, am I right? Of course we also don't use any compiler magic to make it atomic.
Now at such a case, would it cause problems?