"GENERIC constants" in VHDL

is it possible to have different constants depending on the GENERIC input? E.g.:

entity smth is
   generic(
      constant_width : integer := 32
   );
end smth;

architecture Behavioral of smth is
   if(constant_width = 32) then
        constant ROM_tan : rom_type := ( .....
           ....
       );
   else
        constant ROM_tan : rom_type := ( ....
       );
   );

begin
.
.

One workaround is to create two constants and let Vivado trim one away(using generate and if) if it's not used, but that doesn't look elegant. The other one is to concatenate two constants, since in my case the difference between constants is only the size, i.e precision, of the constants depending on the input width, but that’s not very elegant for me either. Is there any other way? (Maybe something with package?)

Kind Regards,

Den