how do sequential assignments to a signal inside a process behave

I'm wondering, how sequential assignments to the same signal inside of a process are treated in VHDL.

I've seen code like the following:

ENTITY some_entity IS
    ...
    ...
END some_entity;

ARCHITECTURE Behavioral OF some_entity IS
    SIGNAL some_signal : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN PROCESS (clk)
    ...
    ...
    IF condition1 THEN
        some_signal <= "01";
    ELSE
        some_signal <= (others => '0');
    END IF;

    IF condition2 THEN
        some_signal <= "10";
    ELSE
        some_signal <= (others => '0');
    END IF;

    IF condition3 THEN
        some_signal <= "11";
    ELSE
        some_signal <= (others => '0');
    END IF;
    ...
    ...
END PROCESS;
...
...
END Behavioral;

At first I thought, that this doesn't really make sense, because some_signal is assigned multiple values at the same time. Vivado is synthesizing it without complaints though and after a little research about processes, I thought it might actually behave equivalent to the following:

ENTITY some_entity IS
    ...
    ...
END some_entity;

ARCHITECTURE Behavioral OF some_entity IS
    SIGNAL some_signal : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN PROCESS (clk)
    ...
    ...
    IF condition3 THEN
        some_signal <= "11";
    ELSIF condition 2 THEN
        some_signal <= "10";
    ELSIF condition1 THEN
        some_signal <= "01";
    ELSE
        some_signal <= (others => '0');
    END IF;
    ...
    ...
END PROCESS;
...
...
END Behavioral;

Is this notion correct? And if not, what does the first code example actually do?