An example, in x86 are Instruction Set to hardware acceleration AES. But are there in x86 any instructions to accelerate SHA (SHA1/2/256/512) encoding, and what library is the fastet to encoding SHA on x86?
4 Answers
2019 Update:
OpenSSL does use H/W acceleration when present.
On Intel's side Goldmont µarch has (Atom-series) and from Cannonlake (desktop/mobile, 10nm) onwards have SHA-NI support, Cascade Lake server CPUs and older do not support it. Yes, support is non-linear on timeline due to parallel CPU/µarch lines present.
In 2017 AMD released their Zen µarch, so all current server and desktop CPUs based on Zen fully support it.
My benchmark of OpenSSL speed SHA256 showed a 550% speed increase with a block size of 8KiB.
For real 1GB and 5GB files loaded to RAM the hashing was roughly 3x times faster.
(Benchmarked on Ryzen 1700 @ 3.6 GHz, 2933CL16 RAM; OpenSSL: 1.0.1 no support vs 1.1.1 with support)
Absolute values for comparison against other hash functions:
sha1 (1.55GHz): 721,1 MiB/s
sha256 (1.55GHz): 668.8 MiB/s
sha1 (3.8GHz) : 1977,9 MiB/s
sha256 (3.8GHz) : 1857,7 MiB/s
See this for details until there's a way to add tables on SO.
CPUID identification, page 298: 07h in EAX → EBX Bit 29 == 1.
Intel's Instruction Set Reference, page 1264ff.
Agner Fog's Instruction tables where he benchmarks instruction latency/µops etc. (currently Zen, Goldmont, Goldmont Plus available)
Code example, SIMD comparison: minio/sha256-simd
Related