Initializing an array of records in VHDL

I have an record defined as follows

type ifx_t is
record
  data                        : std_logic_vector(127 downto 0);
  address                     : std_logic_vector (19 downto 0); 
  WrReq                       : std_logic;-- 
  RdReq                       : std_logic; --
end record;
type Array_ifx_t is array (0 to 2) of ifx_t;

And I have to initialize an instance of this array of records and I have tried the following way and it doesn't work

signal pair_in       : Array_ifx_t:= (others =>((others =>'0'),(others=>'0'),'0','0')); 

Kindly help.