Does SystemVerilog support downcasting?

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Does SystemVerilog support downcasting (casting a base object to a derived object)? If so, how?

The following downcast example does not work:

class base;
  int a = 5;
endclass

class extend extends base;
  int b = 1;
endclass

module test;

  initial begin
    base m_base;
    extend m_extend;

    m_base = new();
    m_extend = new();
    $cast(m_extend, m_base);
    $display(m_extend.a);
  end
endmodule

Modify and rerun the example on EDA Playground: http://www.edaplayground.com/s/4/581

system-verilog casting
3 Answers

In this solution, you are nowhere downcasted, you just use the $cast to check if classes are compatible or not. If yes, print that particular class (DOG in your case) is found.

In you $cast function first parameter (destination) you are taking another_dog as a child class and in the second parameter (source) you are picking from queues that is again queues of child classes

user_49482030
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