Wait until <signal>=1 never true in VHDL simulation

user_922723 0
Viewed 13587

Below is the code that I am running. My question is why doesn't the 3rd wait until trigger in modelsim? The console output is simply GOT HERE. It never gets to the line GOT HERE 2. I would think that having the same wait until <SIGNAL> = 1 twice in a row would be fine because the condition is true both times. I didn't add 'event in there, so I wouldn't think the simulator would need to see the edge. Can anyone explain this behavior?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example_wait_failure is
end example_wait_failure;

architecture behave of example_wait_failure is

  signal r_CLK_TB : std_logic := '0';

begin

  r_CLK_TB <= '1' after 20 ns, '0' after 40 ns, '1' after 60 ns;


  p_TEST : process
  begin

    wait until r_CLK_TB = '1';
    report "GOT HERE" severity note;

    wait until r_CLK_TB = '1';
    wait until r_CLK_TB = '1';
    report "GOT HERE 2 " severity note;

  end process p_TEST;

end behave;
modelsim fpga vhdl
3 Answers

I hang on the same issue.
My possible workaround is to add the global clock to the sensitivity list:

nClk <= NOT nClk AFTER 10 ns;

WAIT ON nClk UNTIL signalToCheck = '1';
user_142072340
Related