Bidirectional databus design

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I need to communicate with a chip via a bidirectional databus (ULPI).

As far as I can ascertain, data is shifted out on the ULPI bus on rising clock edges, and read on falling clock edges. My problem is that when reading a register, I first need to be sensitive to rising edges (to write the command to the chip on the databus), and then to falling edges when reading register output onto the bus from the chip.

I'm unclear as to how to design this the best way.

I tried with one process which had a case statement, but for this to work, my process needs to be sensitive to both rising and falling edges, which I think is not good. Or is it actually OK?

vhdl
2 Answers

I know that this is an very old article but my comment is for people who want to connect/implement ULPI. In ULPI there is no tristate data buffer. Read the chapter 2.3.1 Bus Ownership from "ULPI Interface Specification", if you want to know how transfer/transmit in ULPI must be implemented.

If you write the vhdl in the accepted answer your code wouldn't work all of the time. Some things which you must be care of are:

  • turn around cycle
  • aborting data
user_92040050
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