What' s the difference between <= and := in VHDL

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Currently, I am learning some FPGA design techniques using VHDL, my problem is whether we can use := and <= interchangeably in VHDL or not, though I've seen the use of := in constants declarations and <= in assignments? Thanks in advance!

colon-equals logic vhdl embedded
3 Answers

<=

UseCase: Signal assignments that take place in the next cycle.

Example: signal temp:std_logic_vector

:=

UseCase: Variable assignments that take place immediately.

Example: variable temp:std_logic_vector

Except for adding initial values to signals, you can also use :=.

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