What is the difference between "make" and "make all"?

I have a Makefile with the following structure (working example).

.PHONY: image flashcard put-files

put-files:
    @echo "=== put-files"

image:
    @echo "=== image"

flashcard:
    @echo "=== flashcard"

all: put-files image flashcard
    @echo "Done"

I expect that a simple make would build all three targets, but this is not so:

% make
=== put-files

But if I explicitly specify the target, the dependencies are built as well:

% make all
=== put-files
=== image
=== flashcard
Done

What am I doing wrong?