Error adding std_logic_vectors

user_490076 0
Viewed 70994

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not synthesize. 

library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity add_module is
        port(
  pr_in1   : in std_logic_vector(31 downto 0);
  pr_in2   : in std_logic_vector(31 downto 0);
  pr_out   : out std_logic_vector(31 downto 0)  
        );
end add_module;

architecture Behavior of add_module is

begin

    pr_out <= pr_in1 + pr_in2;

end architecture Behavior;

The error message I get from XST

Line 17. + can not have such operands in this context.

Do I miss a library? If possible, I do not wanna convert the inputs into natural numbers.

Many thanks

fpga vhdl
5 Answers

You cannot do an arithmetic operation with just std_logic_vector. Either you have to convert the std_logic_vector to signed/unsigned (depending on your code requirements) (see 1 below) or else convert them to integers (see 2 below)

  1.      pr_out = std_logic_vector(unsigned(pr_in1) + "01")

  2.      pr_out = std_logic_vector(integer(pr_in1) + 99)

These are just examples. You can change them based on your requirements.

user_101471590
Related