Creating a VHDL backend for LLVM?

user_46190 0
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LLVM is very modular and allows you to fairly easily define new backends. However most of the documentation/tutorials on creating an LLVM backend focus on adding a new processor instruction set and registers. I'm wondering what it would take to create a VHDL backend for LLVM? Are there examples of using LLVM to go from one higher level language to another?

Just to clarify: are there examples of translating LLVM IR to a higher level language instead of to an assembly language? For example: you could read in C with Clang, use LLVM to do some optimization and then write out code in another language like Java or maybe Fortran.

vhdl llvm
7 Answers

Yes !

There are many LLVM back-end targeting VHDL/Verilog around :

And I know there are many others...

The interesting thing about such low-level representations as LLVM or GIMPLE (also called RTL by the the way) is that they expose static-single assignments (SSA) forms : this can be translated to hardware quite directly, as SSA can be seen as a tree of multiplexers...

user_1789250

tl,dr: I don't think LLVM is the right tool

What your are looking for is way to translate LLVM code to a higher language that's what emscripten do for Javascript.

But it looks like you miss a bit the point of LLVM as it's meant to generate static code in order to achieve that they use a specific intermediate language build for that purpose.

As you can see the way emscripten works is by implementing a stack, but without using javascript as a human would have done it.

They are several project that try to achieve what you original question was, like MyHDL that turns python to VHDL or Verilog.

user_1408370
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