Force gnu make to rebuild objects affected by compiler definition

Viewed 8337

I have a makefile that takes options at the command line

make OPTION_1=1

Based on the value it will add additional compiler definitions to a subset of objects.

ifeq ($(OPTION_1), 1)
CC_FLAGS += -DOPTION_1_ON
endif

The change in the definition affects the included header file content - a stub or an implementation is exposed to the object files.

How can I get make to rebuild the files 'affected' by this option changing?

1 Answers
Related