Difference between "||" and "or" in system verilog

Asutosh Mishra 0
Viewed 41

I am trying to wait for a change in 2 signals in following 2 ways.

  Option 1: @(a or b)
  Option 2: @(a || b)

If any change observed for any signal then I am trying to display the value as shown below.

module wait_test;
  int a, b;
  initial
    begin
      #10 a += 10;
      #10 b += 10;
      #10 a += 10;
      #10 b += 10;
    end
   initial
     forever
       begin
         @(a or b)
         $display($time,"\ta = %0d,b = %0d", a, b);
       end
endmodule

Result:

 10 a = 10,b = 0
 20 a = 10,b = 10
 30 a = 20,b = 10
 40 a = 20,b = 20

When I replace @(a or b) with @(a || b), I only observe 1st display with no errors. Please help me with the reason.

Result:

 10 a = 10,b = 0
logical-or system-verilog
1 Answers

The or operator in this context is described in IEEE Std 1800-2017, section 9.4.2.1 Event OR operator. Whenever there is a change in either a or b, the $display statement will be executed, as you have seen.

The || operator is a simple logical OR. It will first evaluate the expression (a || b), then the event control @ syntax will wait for a change in the expression, not the individual signals. At time 0, both signals are 0, which means the expression is 0. At time 10, a changes to 10, which means the expression changes to 1. Although the signals continue to change every 10 time units, the expression remains 1, so there are no further changes in the expression.

@(a || b) is not a typical construct. @(a or b) is a typical construct.

Also, your initial forever block is much more commonly coded as:

always @* begin
    $display($time,"\ta = %0d,b = %0d", a, b);
end
toolic0
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