Double data hazard in MIPS

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According to the book Computer Organization and Design by Patterson and Hennesy (5th ed, page 310):

One complication is potential data hazards between the result of the instruction in the WB stage, the result of the instruction in the MEM stage, and the source operand of the instruction in the ALU stage. For example, when summing a vector of numbers in a single register, a sequence of instructions will all read and write to the same register:

add $1, $1, $2
add $1, $1, $3
add $1, $1, $4

In this case, the result is forwarded from the MEM stage because the result in the MEM stage is the more recent result.

Why is the result forwarded from MEM stage when it is possible to forward the result from the EX stage, like this? (Red lines indicate forwarding paths):

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I have seen a similar question here. The accepted answer corrects MEM-hazard conditions stated in the book, but also tells that both EX-hazard and MEM-hazard occur in the aforementioned instructions. I can only see EX-hazard occurring between the instructions 1,2 and 2,3. How does MEM-hazard occur in these instructions?

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