I coded a for loop inside and always_ff block. This loop's iterator is called i and I initialize it to 0.
My problem is that when I run simulation, it tells me that i stays unitialized, and I get the same problem with two other for loops in my module. Of course this causes everything else to fail.
Here is my code:
module Histogram_File #(
parameter NUMBER_OF_REGISTERS = 8,
parameter DATA_WIDTH = 18
)(
input logic resetN,
input logic clk,
input logic write_enable,
input logic start_of_frame,
input logic [2:0] bin_addr_write,
output reg [DATA_WIDTH-1:0] mem [0:NUMBER_OF_REGISTERS-1],
output reg [DATA_WIDTH-1:0] cdf [0:NUMBER_OF_REGISTERS-1],
output logic [2:0] bin_max
);
int i;
int j;
int k;
always_ff@(posedge clk or negedge resetN) begin
if (!resetN) begin
for (i=0; i<NUMBER_OF_REGISTERS; i++) begin
mem[i] <= {(DATA_WIDTH){1'b0}};
cdf[i] <= {(DATA_WIDTH){1'b0}};
end
bin_max <= 3'b0;
end
else if (write_enable) begin
if(start_of_frame) begin
for (j=0; j<NUMBER_OF_REGISTERS; j++) begin
if(j < bin_addr_write) begin
mem[j] <= {(DATA_WIDTH){1'b0}};
cdf[j] <= {(DATA_WIDTH){1'b1}};
end
else if(j == bin_addr_write) begin
mem[j] <= {(DATA_WIDTH){1'b1}};
cdf[j] <= {(DATA_WIDTH){1'b1}};
end
else begin
mem[j] <= {(DATA_WIDTH){1'b0}};
cdf[j] <= {(DATA_WIDTH){1'b0}};
end
end
bin_max <= bin_addr_write;
end
else begin
mem[bin_addr_write] <= mem[bin_addr_write] + 18'b1;
for(k = 0 ; k<=NUMBER_OF_REGISTERS; k++) begin
if(k < bin_addr_write) begin
cdf[k] <= cdf[k] + 18'b1;
end
end
if(bin_max < bin_addr_write) begin
bin_max <= bin_addr_write;
end
end
end
end
endmodule
And here is my simulation:
I work on the software Quartus Prime Lite Edition.