A while ago I wrote my own ethernet driver for fun, and most of the time was spent banging my head on the keyboard because it wasn't working - as is tradition.
Problem ended up being that ethernet simply couldn't read from or write to AXI SRAM. I made a very long post about it (along with a couple other matters) on st's community thing, that went unanswered and I eventually forgot about it.
The reason I ask here how it is I should have known, is because it doesn't really seem to mention it anywhere. The bus interconnect table and diagrams don't seem to show any potential problem:
And the block diagram:
And maybe the ART isn't what I interpret from this:
but what I interpret is that it serves as an accelerator for the pre-fetching of instructions to be executed by (assumingly) the M4 processor from D1 memory - and to establish a connection to D1 memory in general.
Is this just me not knowing the meaning of the word "access"? English isn't my first language but I'm pretty sure when you "gain access" to something, that means you get to play around with it, so reading and writing.
This has come to mind after so long because now I want to use an SD card for something I'm doing, and I find it necessary to write from D2 memory into the card, and then from the card into D1 memory.
SDMMC1 is out of question since it can't even interact with D2 memory at all, and for SDMMC2 I'm afraid I'll have the same scenario as I did with ethernet.
I realize I can still regular-dma things around, but that's quite a bit of extra complexity and extra memory use.
So - what did I miss that would have let me know I can't ethernet-dma into axi sram? And should I expect it to prevent me from sdmmc2-dma-ing into axi sram as well?
Thank you!