how to include "," comma in SystemVerilog Macros

userpuQl1 0
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There are Argument that contain "," comma inside it for example num,val,int in one Argument.

For example, `define ACTION_DO(num,val,int)

Which are actually meant to pass as one Argument only, is there any way to include the "," comma inside the code and wont get assumed by compiler as 3 Argument separately?

system-verilog macros
1 Answers

Unfortunately, there is no good generic way to deal with a single argument containg commas in macros. There are a couple of possibilities which might or might not fit in your usage mode:

  1. Quoted strings, which are always treated as a single argument,
  2. argument listed within parens or square braces. But in this case parenthesis and braces will be a part of the argument:

The following will work:


`define PRINT(A) $display A
... 
`PRINT(("a=%b, b=%b, c=%b", a, b, c));

It will be expanded to $display ("a=%b, b=%b, c=%b", a, b, c)

The following will fail in compilation

`define PRINT(A) $display("a=%b b=%b c=%b", A)
`PRINT((a, b, c));

because expansion $display("a=%b b=%b c=%b", (a,b,c)) is syntactically wrong.

userOAN40
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