Defer target until variable set

mr.b 0
Viewed 24

I have a project where you can build for multiple platforms, architectures, etc. I need to be able to set various variables based on the target before compiling any source files. But what's happening is the non-platform specific files are getting compiled immediately and then the platform specific ones didn't get compiled at all.

Below calling "make foobar_mac", foo.o gets created but bar.mac.o does not and therefore during the final link bar.mac.o is missing.

OBJS = foo.c bar.$(PLATFORM).c

%.o : %.c
    $(COMPILE.c) $(OUTPUT_OPTION) $<

foobar_mac: PLATFORM := mac
foobar_mac: $(OBJS)

foobar_win: PLATFORM := win
foobar_win: $(OBJS)
gnu-make makefile
1 Answers

There are various ways to get what you want. One way is to use secondary expansion to delay the expansion until after the target-specific variable is in scope.

Like this:

.SECONDEXPANSION:

OBJS = foo.c bar.$$(PLATFORM).c

%.o : %.c
        $(COMPILE.c) $(OUTPUT_OPTION) $<

foobar_mac: PLATFORM := mac
foobar_mac: $(OBJS)

foobar_win: PLATFORM := win
foobar_win: $(OBJS)

Note how we added .SECONDEXPANSION, then we escaped the $(PLATFORM) reference in OBJS as $$(PLATFORM) so it would not be expanded when GNU make parses the makefile.

There are various other ways to do this as well.

MadScientist0
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