VHDL Signal "lights" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.std_logic_1164.STD_LOGIC

 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity traffic_light_hot_testbench is
end traffic_light_hot_testbench;

architecture bevTestbench of traffic_light_hot_testbench is
component traffic_light_hot is 
    port ( 
        clk, rst , carew , carns  : in std_logic;
    
        lights : out std_logic_vector(5 downto 0)
);
end component traffic_light_hot;

signal clk, rst, carew, carns: std_logic := '0';
signal lights: std_logic_vector(5 downto 0) := (others => '0');
constant clk_period : time := 100 ns;

begin
DUT_TLC14_8: traffic_light_hot port map(clk,rst,carew,lights,carns); --14_8
--DUT_TLC14_11: TLC14_11 port map(clk,rst,carew,lights); --14_11

clk_process: process begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
end process;

stim_proc: process
    begin
        wait for 100 ns;
        rst <= '1';
        wait for 100 ns;
        rst <= '0';
        wait for 100 ns;
        carew <= '1';
        wait for 100 ns;
        carew <= '0';
        wait for 500 ns;
        carew <= '1';
   wait;
end process;

end architecture;

I am having this error ** Error: C:/Users/cqthomas/vhdl/new_testbench.vhd(22): Signal "lights" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.std_logic_1164.STD_LOGIC. ** Error: C:/Users/cqthomas/vhdl/new_testbench.vhd(22): Signal "carns" is type ieee.std_logic_1164.STD_LOGIC; expecting type ieee.std_logic_1164.STD_LOGIC_VECTOR.

please help Thank You