I'm reading about virtual memory and I have some doubts reguarding multi-level paging. I saw that in a N-level page table, the N-1 tables are used to store indexes to the next level tables.
This is my point:
Assuming the case of RISC-V Sv39 (Section 4.4 of RISC-V privileged architecture). We have the physical address of 1-level page root in SATP.ppn.
Virtual address is composed as follows:
<38-29> VPN[2] (9 bits)
<28-21> VPN[1] (9 bits)
<20-12> VPN[0] (9 bits)
<11-0> offset (12 bits)
After a TLB-miss, a page walk starts:
- index_to_second_level_PT = SATP.PPN + VPN[2]
- index_to_third_level_PT = index_to_second_level_PT + VPN[1]
- physical_address = index_to_third_level + VPN[0]
My questions is: Do all the idexes in the PTE (i.e, computed in step 1., 2., and 3.) are physical addresses? this makes sense to me, since once we get the physical address of the next table we can retrieve it from physical memory.
Moreover, always in RISC-V manual, also physical addresses and PTE entries are formatted with multiple fields (PPN[0], PPN[1], and PPN[2]). I understand that the virtual address is partitioned into three 9-bit fields to index the multi-level page table, but I don't understand why also the physical address is partitioned in such way.
Thanks in advance to anyone who responds.