Timing Summary:
Speed Grade: -1
Minimum period: 4.979ns (Maximum Frequency: 200.844MHz) Minimum input arrival time before clock: 1.459ns Maximum output required time after clock: 0.833ns Maximum combinational path delay: No path found This is obtained from xilinx 14.7 same cannot be found in xilinx vivado and by adding constraint wizard and calculating 1/(T-WNS ) = MAX Frequency is too low when compared with same programs in two different tool (but same hardware and same program)