Simulation problem : I never get into the loop

i got some question about my simulation in vhdl. I don't know why i never enter into the loop "if (voltage_i < ir_average) then" whereas voltage_i is lower than ir_average.

Here is the code :

library IEEE;
library work;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.type_package.all;
use work.bench_package.all;
use work.pkg_tool_box.all;


entity VOLTAGES is
  generic  (
    VOLT_RAMP_DEF          : integer;
    RATIO                  : integer;
    ADC_SIZE               : integer;                               -- ADC's size
    ID_LANE                : std_logic_vector(3 downto 0));         -- group assigned to the voltage
    --ADC_VOLTAGE            : real;
  port   (
    EN                     : in  std_logic_vector( 7 downto 0); 
    TH                     : in  t_th_vlt; -- IRL, IRH, OBZ  
    TIMER_SEL_GRP          : in  t_prescaler_sel_F; 
    TIMER_CNT_GRP          : in  t_prescaler_cnt_F; 
    FORCE_EN               : in  std_logic;
    FORCE_VALUE            : in  real range 0.00 to 5.0;
    VOLTAGE                : out real range 0.00 to 5.0);
end VOLTAGES;

architecture RTL of VOLTAGES is
  constant ADC_DEF         : real    := real(2**ADC_SIZE)/3.3;
  constant EN_GRP          : integer := to_integer(unsigned(ID_LANE));
  signal   voltage_i       : real    range 0.0 to 5.0 := 0.0;
  signal   ir_average      : real := 0.0;
  signal   obz_half        : real := 0.0;
  signal   volt_increment  : real := 0.0;
  signal   ir_volt_increment  : real := 0.0;
  signal   obz_volt_increment  : real := 0.0;
  signal   delay_increment : time := 0 us;
  signal   delay_decrement : time := 0 us;
  signal   temp            : integer := 0;
  signal   temp1           : real := 0.0;
  signal   irl_integer     : integer := 0;
  signal   irl             : integer := 0;
  signal   irh             : integer := 0;
  signal   obz             : integer := 0;
  signal   irh_real        : real := 0.0;
  signal   irl_real        : real := 0.0;
  signal   obz_real        : real := 0.0;
begin

  VOLTAGE         <= FORCE_VALUE when (FORCE_EN = '1') else voltage_i;
  --temp            <= to_integer( to_integer(unsigned(TH(0)))+to_integer(unsigned(TH(1))) );
  irl             <= to_integer(unsigned(TH(0)));
  irh             <= to_integer(unsigned(TH(1)));
  irh_real        <= real(irh);
  irl_real        <= real(irl);
  ir_average      <=(irh_real + irl_real)/(2.0*ADC_DEF);
  --ir_average      <= real(to_integer( unsigned(TH(0))+unsigned(TH(1)) )); --/ (2.0);--*ADC_DEF);     -- (IRL + IRH)/(2.0*4096)
  obz             <= to_integer(unsigned(TH(2)));
  obz_real        <= real(obz);
  obz_half        <= obz_real/(2.0*ADC_DEF);

  --obz_half        <= real(to_integer(unsigned(TH(2)))) / (2.0*ADC_DEF);                       -- (OBZ)/(2.0*4096)
  --volt_increment  <= ir_average / real(VOLT_RAMP_DEF);

  ir_volt_increment  <= ir_average / real(VOLT_RAMP_DEF);
  obz_volt_increment <= obz_half / real(VOLT_RAMP_DEF);

  delay_increment <= (10 us * 2**(to_integer(unsigned(TIMER_SEL_GRP( EN_GRP )(UP  ))))* to_integer(unsigned(TIMER_CNT_GRP( EN_GRP )(UP  ))) * RATIO) / VOLT_RAMP_DEF;
  delay_decrement <= (10 us * 2**(to_integer(unsigned(TIMER_SEL_GRP( EN_GRP )(DOWN))))* to_integer(unsigned(TIMER_CNT_GRP( EN_GRP )(DOWN))) * RATIO) / VOLT_RAMP_DEF;

  voltage_process: process is
    begin

      -- Rising condition: EN asserted and voltage under average of IRL+IRH
      if    (EN(EN_GRP) = '1') then
        --if ((voltage_i + ir_volt_increment) < ir_average) then
        if (voltage_i < ir_average) then
          wait for delay_increment;
          voltage_i <= voltage_i + ir_volt_increment; -- increment
        else
          voltage_i <= ir_average;                 -- set final value
          wait until EN(EN_GRP)'event;             -- stable state
        end if;

      -- Falling condition: EN de-asserted and voltage over half of OBZ
      else --> EN(EN_GRP) = '0'
        if ((voltage_i - obz_volt_increment > obz_half)) then
          wait for delay_decrement;
          voltage_i <= voltage_i - obz_volt_increment; -- decrement
        else
          voltage_i <= obz_half;                   -- set final value
          wait until EN(EN_GRP)'event;             -- stable state 
      end if;
    end if;

--    wait until EN(EN_GRP)'event;

  end process voltage_process;

end RTL;

enter image description here

As you can see on the simulation, voltage_i is always equal to 0, and 0 is lower than 2.09473 so i really don't know where the problem comes from.

Thank you for your help.