Difference between declaring signal in architecture and in entity

yeuop 0
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Assuming that I have the following piece of code:

entity MyEntity is
  port  (
    i_clock      : in  std_logic;         -- these are the signals inside entity
    Clk_100HZ    : inout  std_logic;
    Data         : inout  std_logic;
    );
end MyEntity;

architecture rtl of MyEntity is
  signal D_zeroin            : std_logic; -- these are the signals inside architecture
  signal D_onein             : std_logic;
  signal D_twoin             : std_logic;
  signal D_threein           : std_logic;

begin
...

What is the difference between signals declared in port's entity and signals declared directly into architecture?

vhdl
1 Answers

Declarations in the entity can be of ports or generics. Generics are constants fixed at compilation time. Ports input and/or output signals from the architecture to the instantiating architecture i.e. the 'next level up'.

Signals are nodes/registers/memory within the architecture itself that cannot be seen by any architectures outside.

The parallel often given is that of a logic chip IC on a circuit board:

  • The entity specifies the pins on the IC that signals flow through, in and out of the chip to the board.
  • The architecture is the chip circuit inside the IC package. Its internals cannot be accessed.
  • Instantiating a component is plugging one of that IC into a circuit board.

The publicly-known entity will be visible to the architecture above that instantiated that component.

But the architecture is hidden away with its contents not visible to any other part of the design and not necessarily visible to the people using the component. Different architectures can be designed and associated with the entity for compilation.

userDwCj0
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