Writing this selected signal assignment in a more compact way

gorilla_glue 0
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I have an 8-bit signal all_inputs that I am feeding into a selected signal assignment on a signal W1, as shown below:

with all_inputs select W1 <=
    '1' when "010001",
    '1' when "100100",
    '1' when "001100",
    '0' when others;

I want to know if there is a way to combine the string literals into one line to write it more compactly. If I had more signal values to add, it would get tedious quickly. I've tried:

with all_inputs select W1 <=
    '1' when "010001" or "100100" or "001100",
    '0' when others;

Which does synthesize, but seems to treat the expression as a bitwise OR operation, where I want a logical treatment of these values. Surrounding the string literals with ()s gives me a syntax error.

Any ideas on how I can make these assignments a little more compact?

vhdl
1 Answers

This answer has exactly what I was looking for - the | (pipe/vertical bar) operator:

The delimiter vertical bar ('|') is used to separate choices.

So, changing this:

with all_inputs select W1 <=
    '1' when "010001" or "100100" or "001100",
    '0' when others;

to this:

with all_inputs select W1 <=
    '1' when "010001" | "100100" | "001100",
    '0' when others;

Now sets W1 to 1 when all_inputs is any of the three provided string literals,

rather than

when all_inputs is the bitwise-OR of those signals.

gorilla_glue0
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