So. A normal full adder that have 3 inputs
A, B, Ci (carry in) and 2 outputs S (Sum), Co (Carry-out). After doing truthtable and K-map we get the function for S as: S = A ⊻ B ⊻ Ci and the function for Co as: AB ∨ Ci(A ⊻ B)
Now when we are realizing this in gate-form S is pretty simple. 2 XOR gates where one with inputs A and B are connected to a second one. However, we are supposed to NOT use AND gates in this realization and in the Co function I can't solve on how to design the circuit. We are not told we can't use NAND gates, so that is a possibility. Is that the only way to solve it?
