I'm still relatively new to the STM32 family (a couple months now, previously worked exclusively in ARM7 family). I'm working on a very time constrained code. All is coded in GAS, no C, no OS. I'm using the STM32F730Z8, and clocking it at 200 MHz. All code is copied into ITCM SRAM at boot and executed from there for speed (VTOR maps the vector table appropriately as well).
The problem is that I'm getting double calls to interrupt handlers. I have searched here and on the ST knowledge base, and see a few references, but what they suggest doesn't fix it.
A minimized example is to set the clocking to 200 MHz, enable only TIM7 interrupts. TIM7 is setup by:
write TIM7_CNT,0
write TIM7_PSC,9
write TIM7_ARR,99
write TIM7_DIER,1
write TIM7_CR1,1
The TIM7 handler looks like:
push {lr}
write GPIOD_BSRR,1<<13
write TIM7_SR,0
b <label> to jump over a bunch of crap
write GPIOD_BSRR,1<<29
POP {pc}
"write" is just a simple macro:
.macro write addr, value
ldr r1,=\addr
ldr r0,=\value
str r0,[r1]
.endm
The use of PD13 is as a timing fiducial -- I look at that pin on my scope. What I see is pairs of pulses. They are properly 10us apart, so each pair is produced by a single reload of TIM7. Each pair consists of two 25ns pulses with a gap of 100ns between.
This is unacceptable. I need to have only a single call to the handler on each timer tick. I've tried writing twice to TIM7_SR to clear the UIF bit. I've tried writing to TIM7_SR at entry to the handler and at exit. I've tried clearing the pending bit in NVIC_ICPR1. I've tried inserting extra nonsense code to give it more time to propagate the clearing action. I can't believe that there is no fix for this. Help!?!
Jeff Casey / Rockfield Research Inc. / casey@rockfieldresearch.com / Las Vegas, NV