ARM ABI says that the stack should be 8-byte aligned, but I see cases where the stack is aligned only to 4-byte boundary.
For example, I have the following simple busy-delay function:
void delay(int iter) {
int volatile counter = 0;
while (counter < iter) { // delay loop
++counter;
}
}
This compiles with IAR EWARM 9.10.2 on ARM Cortex-M to the following disassembly:
SUB SP, SP, #0x4
...
ADD SP, SP, #0x4
BX LR
The problem is that after SUB SP,SP,4 the stack is misaligned (is aligned only to 4-byte boundary).
Why is this happening? Is this compliant with the ARM ABI? Are there any compiler options to control that?
This question is related, but not a duplicate of: Aligning a Stack pointer 8 byte from 4 byte in ARM assembly