A problem about bidirectional constraint on system-verilog randomizing

I tried to use bidirectional constraint to randomize int a and b. However, the two constraints "a inside {'{1,2,3,4}}" and "a==0->b==0" seem contradictory, because the rand int a and b cannot be randomized correctly. The simulation tools are ModelSim and Vivado, and both failed to randomize the variables. Besides, I wonder why "a inside {array}" need "{}" outside the "array". Is that because the usage of the keyword "inside" in system-verilog? The system-verilog code is shown below, and I'm looking forward to your reply.

`timescale 1ns / 1ps

class rand_int;
    rand int a, b;
    int array [];
    
    function new(
        input int int_array []
    );
        array = int_array;
    endfunction
    
    constraint c1{ 
        a inside {array};
        a==1 -> b==0; 
    }

endclass


module tb__bidirectional_constraint;

int array [];
rand_int Rand_Int;

initial begin
    array = new[4] ('{1,2,3,4});    
    Rand_Int = new(array);
    repeat(100)begin
        assert(Rand_Int.randomize())
            $display("a==%0d, b=%0d",Rand_Int.a,Rand_Int.b);
    end
end


endmodule