Euclidean Distance Calculation VHDL

is there any solution for this

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Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:26 . Memory (MB): peak = 1678.414 ; gain = 11.855
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INFO: [Synth 8-638] synthesizing module 'dist3d' [D:/Vivado/test_abs/test_abs.srcs/sources_1/new/dist3d.vhd:19]
WARNING: [Synth 8-7193] Integer conversion function is truncating input [D:/Vivado/test_abs/test_abs.srcs/sources_1/new/dist3d.vhd:58]
ERROR: [Synth 8-502] non-constant real-valued expression is not supported [D:/Vivado/test_abs/test_abs.srcs/sources_1/new/dist3d.vhd:58]
ERROR: [Synth 8-285] failed synthesizing module 'dist3d' [D:/Vivado/test_abs/test_abs.srcs/sources_1/new/dist3d.vhd:19]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;  
entity dist3d is
    generic(g_bitwidth : integer := 16);
    port(i_clk      : in    std_logic;
         i_dv       : in    std_logic;
         i_x1       : in    std_logic_vector(g_bitwidth-1 downto 0);
         i_y1       : in    std_logic_vector(g_bitwidth-1 downto 0);
         i_z1       : in    std_logic_vector(g_bitwidth-1 downto 0);
         i_x2       : in    std_logic_vector(g_bitwidth-1 downto 0);
         i_y2       : in    std_logic_vector(g_bitwidth-1 downto 0);
         i_z2       : in    std_logic_vector(g_bitwidth-1 downto 0);
         o_dv       : out   std_logic;
         o_dist     : out   std_logic_vector(g_bitwidth-1 downto 0)      
    );
end entity dist3d;
architecture rtl of dist3d is
    -- Output = sqrt{ (x_1-x_2)^2 + (y_1-y_2)^2 + (z_1-z_2)^2 }
    -- Pipline Stage 1 - Difference
    signal f_x_diff : signed(g_bitwidth-1 downto 0) := (others => '0');
    signal f_y_diff : signed(g_bitwidth-1 downto 0) := (others => '0');
    signal f_z_diff : signed(g_bitwidth-1 downto 0) := (others => '0');
    
    -- Pipline Stage 2 - Squaring
    signal ff_x_sq  : signed(2*g_bitwidth-1 downto 0) := (others => '0');
    signal ff_y_sq  : signed(2*g_bitwidth-1 downto 0) := (others => '0');
    signal ff_z_sq  : signed(2*g_bitwidth-1 downto 0) := (others => '0');
    
    -- Pipline Stage 3 - Addition
    signal fff_xy   : signed(2*g_bitwidth-1 downto 0) := (others => '0');
    signal fff_z    : signed(2*g_bitwidth-1 downto 0) := (others => '0');
    
    -- Pipline Stage 4 - Addition
    signal f4_dist  : signed(2*g_bitwidth-1 downto 0) := (others => '0');
    signal TEMP     : signed(g_bitwidth-1 downto 0);
    signal TEMP_F4  :real;
begin
    p_calc : process(i_clk)
    begin
        if rising_edge(i_clk) then
        f_x_diff <= signed(i_x1) - signed(i_x2);
        f_y_diff <= signed(i_y1) - signed(i_y2);
        f_z_diff <= signed(i_z1) - signed(i_z2);
        
        ff_x_sq  <= f_x_diff * f_x_diff;
        ff_y_sq  <= f_y_diff * f_y_diff;
        ff_z_sq  <= f_z_diff * f_z_diff;
      
        fff_xy   <= ff_x_sq + ff_y_sq;
        fff_z    <= ff_z_sq;
            
        f4_dist  <= fff_xy + fff_z;   
     end if;
    end process;

TEMP_F4 <= real(to_integer(f4_dist));
TEMP <= to_signed(integer(sqrt(TEMP_F4)),16);
o_dist <=  STD_LOGIC_VECTOR(TEMP);

end rtl;