What will happen if I read and write a register both at the posedge of the clock cycle? I encountered this question while learning a RISC-V pipeline implementation which uses the technique called double bump to avoid this question. I wonder why this is necessary to split the write and read of an register.
1 Answers
Already solved. Because 5-stages pipeline I designed launch instruction at posedge, and at negedge the result in the WT stage can be read into register file. Thus it is just a way to save a stall. I misunderstood that at first.
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