Why load cant not forward?

Mr.Knife 0
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Computer organization and design ch4 say:

R-type follow load can not forward, need to stall.

But why?

For example

lw  |F|D|E|M|W
add | |F|D|E|M|W

We can simply forward data from mem_read_data to alu_src.

I guess that's because critical path is too long, pipeline will be meaningless?

So the forward source can only be data from pipeline stage?

Then, there is a new problem, what about R-type before branch at ID stage?

add |F|D|E|M|W
beq | |F|D|E|M|W

If forward source can only from pipeline register, this can not forward, need stall as lw does?

cpu-architecture mips assembly
1 Answers

Just guessing here, but memory is the last stage before write back. Memory happens after execute, so if an instruction right after a load tries to use the result of the load, it has to stall for one cycle even with forwarding as the memory operation is performed one cycle later than an ALU operation would be.

However, with this being the case, there just isn't any point in having the forwarding logic. The next cycle, the result is already in the write-back stage, so it is available for other instructions in the same cycle. Forwarding wouldn't eliminate any bubbles here; in a certain sense, the write-back stage does the forwarding for you.

fuz0
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