x86-64

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Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
user_104619730
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5
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449
x86-64 intel x86 cpu-architecture cpu
Is it possible to mitigate branch misprediction penalty by giving earlier hint?
user_29450270
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2
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48
branch-prediction x86-64 x86
Push/pop around a call on x86_64 (SysV ABI)
user_10847740
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2
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39
x86-64 calling-convention assembly c
An i386/x64 pop FS/GS instruction supports a variant where it increments the SP by 32 bits or 64 bits in stead of 16 bits. What is it used for?
user_57404160
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8
1
116
i386 x86-64 x86 assembly
Differences in custom and std fetch_add on floats
user_48324990
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3
0
88
x86-64 assembly gcc c++
Best way to do a packed 16 element blend using SSE
user_31638310
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9
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258
x86-64 sse intel x86 assembly
How can one figure out if a loop is being entered with a 16 byte aligned address in x86-64 assembly?
user_56262900
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2
1
166
x86-64 micro-optimization memory-alignment assembly optimization
Why does gcc use stack area without decrementing stack pointer?
user_116869130
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2
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47
red-zone x86-64 assembly gcc c
Does rcx always point to the PEB at the process entrypoint?
user_38213000
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5
1
435
x86-64 assembly winapi c windows
Does intel have a separate instruction set for it's GPU
Admin1
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9
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1136
x86-64 instruction-set opengl intel gpu
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