x86-64

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Why does gcc use btq in conjunction with btcq when conditionally set a bit in a uint64_t * memory region
user_113221310
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5
0
145
x86-64 micro-optimization assembly gcc c
Can't modify assembly in x64dbg
user_90462670
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2
2
4324
x64dbg x86-64 disassembly assembly debugging
Why does division by 3 require a rightshift (and other oddities) on x86?
user_57404280
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34
4
2230
integer-division x86-64 compilation assembly c++
How can memory destination BTS be significantly slower than load / BTS reg,reg / store?
user_113221310
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5
1
175
microcoding x86-64 assembly cpu-architecture performance
The x86 disassembly for C code generates: orq $0x0, %(rsp)
user_89819680
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2
3
816
x86-64 callstack assembly gcc c
Test of 8 subsequent bytes isn't translated into a single compare instruction
user_5800830
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4
3
91
memcmp x86-64 optimization comparison c++
Is it legal to have same register as operands in one instruction?
Admin1
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2
2
382
instructions x86-64 instruction-set assembly
Why are x86-64 C/C++ compilers not generating more efficient assembly for this code?
user_13014450
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5
1
125
x86-64 initialization c++ performance
Bottleneck when using indexed addressing modes
user_104619730
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3
1
172
addressing-mode x86-64 micro-optimization intel cpu-architecture
Perf shows L1-dcache-load-misses in a block with no memory access
user_82769730
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2
1
516
perf x86-64 profiling linux performance
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