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How to detect P/E-Core in Intel Alder Lake CPU?
user_5313272
0
•
asked Nov 13, 2021
2
1
810
cpuid
cpu-cores
intel
x86
Can two fuseable pairs be decoded in the same clock cycle?
user_17187836
0
•
asked Nov 12, 2021
5
1
205
intel
x86
assembly
cpu-architecture
cpu
Metal GPU frame time behaves unintuitively
user_1810160
0
•
asked Nov 11, 2021
5
2
313
metal
objective-c++
intel
gpu
macos
Intel-Compiler fails C++14-check with `attribute "__malloc__" does not take arguments`
user_2546099
0
•
asked Oct 1, 2021
2
1
1309
icc
c++14
intel
c++
Is there a difference between SVML vs. normal intrinsic square root functions?
user_16558006
0
•
asked Sep 28, 2021
3
1
230
intrinsics
sse2
sse
intel
c++
Why does L2 hardware prefetcher perform worse with only 1 KiB or 2 KiB access size?
user_11338006
0
•
asked Sep 27, 2021
2
1
190
prefetch
intel
x86
cpu-architecture
performance
Intel MPI 2019 always using gcc version 4.9.3
user_14272134
0
•
asked Sep 17, 2021
2
1
111
intel-mpi
mpi
intel
compilation
gcc
Setup Intel One API framework on MacOS - how to decrease the loading time of conda when I do "source /opt/intel/oneapi/setvars.sh"
user_1773603
0
•
asked Sep 13, 2021
2
0
260
conda
intel
zsh
terminal
python
Where has Intel documented the encoding of extended registers (R8-R15) in ModR/M byte?
user_16708099
0
•
asked Aug 19, 2021
3
1
191
instruction-encoding
x86-64
machine-code
intel
assembly
CPU count for Xeon processor confusion
Admin
1
•
asked Aug 15, 2021
1
2
129
intel
cpu-architecture
python-3.x
python
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