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How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent
user_224132
0
•
asked Aug 13, 2017
46
2
3304
micro-optimization
intel
x86
assembly
cpu-architecture
Optimizing fortran code with intel VTune analyzer
user_1537990
0
•
asked Aug 1, 2017
3
0
243
intel-vtune
performance-testing
intel
fortran
optimization
Efficient bit field extraction from bytes array being interpreted as a bitstream, possibly using Intel's BMI Set 1
Admin
1
•
asked Jul 27, 2017
5
0
229
bit-manipulation
intel
vb.net
algorithm
Intel python and intel environment in anaconda difference?
user_7870674
0
•
asked Jul 24, 2017
3
2
3441
intel-python
anaconda
environment
intel
python
Why is the x86 CR1 control register reserved?
user_3241487
0
•
asked Jul 24, 2017
10
1
1136
intel
x86
cpu-architecture
Why is 1's complement still used for encoding vector instructions?
user_1048186
0
•
asked Jul 21, 2017
3
1
236
ones-complement
twos-complement
x86-64
machine-code
intel
Was there a P4 model with double-pumped 64-bit operations?
user_149138
0
•
asked Jul 12, 2017
5
1
750
x86-64
intel
x86
cpu-architecture
Is lldb working with fortran?
user_1537990
0
•
asked Jul 8, 2017
3
1
1479
lldb
intel
fortran
macos
debugging
How does the NEG instruction affect the flags on x86?
user_1455016
0
•
asked Jun 30, 2017
12
1
4898
negation
twos-complement
intel
x86
assembly
Compiler optimization: g++ slower than intel
user_1430274
0
•
asked Jun 5, 2017
15
2
4091
compiler-optimization
g++
intel
c++
performance
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