assembly

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What does "nop dword ptr [rax+rax]" x64 assembly instruction do?
user_8437320
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20
3
8790
no-op x86-64 assembly cpu-architecture visual-studio
How to "NOT" a register in mips assembly
user_74165210
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3
2
4386
mips bitwise-operators bit-manipulation boolean-logic assembly
Optimizing a bit-manipulating algorithm in GameBoy Z80
user_701750
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13
2
702
z80 gameboy bit-manipulation assembly
Unusual byte sequence to set R8 to 128
user_959540
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3
0
129
x86-64 assembly
Tracing instruction execution from startup
user_80124220
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3
1
103
x86-16 bootloader x86 assembly
Understanding the auipc+jalr sequence used for function calls
user_2393370
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5
1
4248
riscv assembly
Incorrect return address is POPed after SVC call
user_42532290
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4
0
112
cortex-a arm abort assembly stack
Does `isync` prevent Store-Load reordering on CPU PowerPC?
user_15580370
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6
1
1255
powerpc concurrency assembly multithreading
What do the E and R prefixes stand for in the names of Intel 32-bit and 64-bit registers?
user_3036850
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38
1
8566
x86-64 cpu-registers x86 assembly 64-bit
Why doesn't this short comparison optimize the way I expected?
user_13664310
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8
1
249
assembly optimization c++
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