Random value generator in VHDL returns the same value each time

user_19756947 0
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I am trying to generate some random values (only 1 and 0) for a VHDL testbench. I've tried the following code:

impure function rand_int(min_val, max_val : integer) return integer is
  variable r : real;
  variable seed1, seed2 : integer := 999;
begin
  uniform(seed1, seed2, r);
  return integer(round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
end function;

But it only seems to be giving 1, and never 0. Where am I doing wrong?

vhdl random function
1 Answers

When the variable seed1, seed2 : integer := 999; is inside the function, then the same values is used for every call of the function, thus you get the same return value.

Move the variables outside the function, like shown below.

That is also the reason that the function is declared as impure, since some arguments are provided in context, instead of by call.

process is
    variable seed1, seed2 : integer := 999;
    impure function rand_int(min_val, max_val : integer) return integer is
      variable r : real;
    begin
      uniform(seed1, seed2, r);
      return integer(round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
    end function;
  begin
    -- Run for a while
    for i in 0 to 49 loop
      report "Random value: " & integer'image(rand_int(0, 1));
    end loop;
    -- End of simulation
    wait;
  end process;
user_23520820
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