Where are the peripherals register in STM32? are they in the cortex-m core or in the peripheral unit itself?

user_9184900 0
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I have two questions. memory region of the cortex-m core cpu 1- is the memory of the stm32 microcontrollers inside the cortex-m core or outside of it? and if it is inside the cortex-core why is it not shown in the block diagram of the cortex-m core generic user guide?block diagram of the cortex-m core

2-I'm trying to understand the stm32 architecture but I'm facing an ambiguity. usart block diagram

as you can see in the picture the reference manual says that the USART unit has some registers(i.e Data Register). but these registers also exist in the memory region of the cortex-m core(if the answer to the first question is "inside").where are they really? are there two registers for each register? or are they resided in the cortex-m core or in the peripheral itself? is it related to the memory-mapped i/o definition?

cortex-m stm32
3 Answers

The only storage that's inside the CPU core is the registers (including general-purpose and special-purpose registers). Everything else is external, including RAM and ROM.

The peripheral control registers exist, essentially, inside the peripheral. However they are accessed by the CPU in the same way that it accesses RAM or ROM; that's the meaning of the memory map, it shows you which addresses refer to RAM, ROM, peripheral registers, and other things. (Note that most of the memory map is unused - a 32-bit address space is capable of addressing 4GB of memory, and no microcontroller that I know of has anything like that much storage.) The appropriate component 'responds' to read and write requests on the memory bus depending on the address.

For a basic overview the Wikipedia page on memory-mapped IO is reasonably good.

Note that none of this is specific to the Cortex-M. Almost all modern microprocessor designs use memory mapping. Note also that the actual bus architecture of the Cortex-M is reasonably complex, so any understanding you gain from the Wikipedia article will be of an abstraction of the true implementation.

user_6053070

Look at the image below, showing the block diagram of an STM32 Cortex-M4 processor. I have highlighted the CPU Core (top left); and other components you can find inside the microcontroller.

block diagram (partial)

The CPU "core", as its name implies, is just the "core"; but the microcontroller also integrates a Flash memory, a RAM, and a number of peripherals; almost everything outside the core (except debugging lines) is accessed by means of the bus matrix, this is equally true for ROM, RAM, and integrated peripherals.

Note that the main difference between a "microprocessor" and a "microcontroller" is that a the latter has dedicated peripherals on board.

Peripherals on STM32 devices are accessed by the CPU via memory-mapped I/O, look at the picture below:

Memory mapped I/O

As you can see, despite a linear address space from 0x00000000 to 0xFFFFFFFF, the address space is partitioned in "segments", f.e., program memory starting at 0x00000000, SRAM at 0x20000000, peripherals at 0x40000000. Specific peripheral registers can be read/written by pointers at specific offsets from the base address.

For this device, USARTS are mapped to APB1 area, thus in address range 0x40000000-0x4000A000. Note that the actual peripheral addresses can be different from device to device.

user_32798150

Peripherals are connected to core via buses. The address decoder knows which address is handled by the particular bus.

Not only peripherals are connected via buses. Memories are connected the same way. Busses are interconnected via the bridges. Those bridges know how to direct the traffic.

From the core point of view the peripheral register works the same way as the memory cell.

What about the gaps. Usually if the address decoder does not understand the address it will generate the exception - hardware error (in the ARM terminology called HardFault)

Details are very complicated and unless you are going to design your own chip not needed for the register level programmer.

user_61100940
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