I have a c++ project in which i need to define a variable in some CXX files. I have nearly 800 files out of which i need to define a variable for 200 files. So i was thinking to define it in makefile. So how can we do that.
4 Answers
Just add -Dxxx=yy on the command line (xxx the name of the macro and yy the replacement, or just -Dxxx if there is no value).
It's not a Makefile command, it's part of the compiler command line options.
Let's say you want a replacement for #define MYDEF
In your makefile you have the compiler command line, something like (simplest example):
g++ -o myfile.cpp
To get that #define for every myfile.cpp just use -D like so:
g++ -DMYDEF -o myfile.cpp
I would add the compiler flag to set a macro (-D for GCC) to the standard variable CXXFLAGS so it will be applied to any implicit rule compiler invocations:
CXXFLAGS += -DMY_DEFINE
Then add that variable to any explicit rules you may have:
target: source.cpp
$(CXX) -std=c++14 $(CXXFLAGS) ...
Because the standard variables are only added with implicit rules.
Use can use a header file
defining.h:
#define deff 10
main.cxx or any file where you want to use
#include "definitions.h"
The other way is while compiling give following arg g++ -DMYDEF file1.cpp file2.cpp ------ file200.cpp -o abc.exe
Related