BlackBox feature in chisel3

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I want to have a try about BlackBox feature in chisel, but I got below warning infomation and can't pass peak/poke test:

Total FIRRTL Compile Time: 237.8 ms
WARNING: external module "BlackBoxSwap"(swap:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
file loaded in 0.398085417 seconds, 25 symbols, 15 statements

Source code is as below: package gcd

import chisel3._
import chisel3.util._

class BlackBoxSwap extends BlackBox with HasBlackBoxInline  {
//class BlackBoxRealSwap extends BlackBox with HasBlackBoxResource {
  val io = IO(new Bundle() {
    //val clk = Input(Clock())
      //val reset = Input(Bool())
    val out2 = Output(UInt(16.W))
    val out1 = Output(UInt(16.W))
    val in2 = Input(UInt(16.W))
    val in1 = Input(UInt(16.W))
  })


  //setResource("/real_swap.v")

  setInline("BlackBoxSwap.v",
    s"""
       |module BlackBoxSwap (
       |  input  [15:0] in1,
       |  input  [15:0] in2,
       |  output [15:0] out1,
       |  output [15:0] out2
       |);
       |
       |assign out1 = in2;
       |assign out2 = in1;
       |
       |endmodule
    """.stripMargin)

}

/**
  * Compute GCD using subtraction method.
  * Subtracts the smaller from the larger until register y is zero.
  * value in register x is then the GCD
  */
class GCD extends Module {
  val io = IO(new Bundle {
    val value1        = Input(UInt(16.W))
    val value2        = Input(UInt(16.W))
    val loadingValues = Input(Bool())
    val outputGCD     = Output(UInt(16.W))
    val outputValid   = Output(Bool())
  })

  val x  = Reg(UInt())
  val y  = Reg(UInt())

  val swap = Module(new BlackBoxSwap)

  when(x > y) { x := x - y }
    .otherwise { y := y - x }

  when(io.loadingValues) {
    //x := io.value1
    //y := io.value2
    swap.io.in1 := io.value1
    swap.io.in2 := io.value2

    x := swap.io.out1
    y := swap.io.out2
  }

  io.outputGCD := x
  io.outputValid := y === 0.U
}

And I checked generated RTL, it seems it's right. could you help on this ? Thanks a lot!

2 Answers

It looks to me like you are trying to use the firrtl-interpreter backend with a verilog black box. A verilog black box can only be used with a verilog based backend like verilator or VCS. If it's not clear to you how to set the backend look for examples in the chisel-template.

There is a way to use black box simulation with the firrtl-interpreter backend but it would require that you write a scala implementation of the black box.

Chisel3 has several backends, each generates own output. Chisel 3.1 has default backend treadle, so If you need to incorporate your Verilog, do the following:

sbt "test:runMain gcd.GCDMain --is-verbose --backend-name verilator"

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