Create a variable in a makefile by reading contents of another file

GNU make version 4.2 supports file reading operation, so with respect to Maxim Egorushkin's great answer there is an optional way to solve this problem now:

FILE     := test.txt
variable :=$(file < $(FILE))

Much simpler since $(file op filename) was added:

VARIABLE = $(file < my_file.txt)

Manual page here: https://www.gnu.org/software/make/manual/html_node/File-Function.html#index-file_002c-reading-from

If you are using GNU make, another way to get this effect is to use a make "include" of another makefile:

From Makefile:

include "./MyFile.mak"

Create a file "MyFile.mak" with content:

FILE := "my file content"
FILE += "more content 1"
FILE += "more content 2"

Here's a more portable solution, which works with MAKE version 3, where file directive isn't available. The downside is that it requires creating a temporary file in the process.

$(shell echo define my_variable > file.tmp)
$(shell cat my_file.txt >> file.tmp)
$(shell echo endef >> file.tmp)
include file.tmp

The main idea is to use define directive, which is specifically designed to declare multiline variables. Of course, you can avoid using shell and a temporary file if you can explicitly write file contents for Makefile usage.

Keep in mind that, if your file contains $ signs, MAKE will try to expand them as variables/directives when my_variable is expanded (or when assigned, of you define it with :=). If you want to avoid it, you need to escape them before including file contents. For example, instead of cat you can do this:

$(shell sed 's/\$$/$$$$/g' my_file.txt >> file.tmp)