Understanding SPI CPOL and CPHA

TheBestPlayer 0
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I have been studying about SPI and would like to clarify few more things:

1. I am trying to understand about CPOL and CPHA in particular: enter image description here

I have a device (MCP41 that I want to write SPI drivers for). The datasheet can be found here: https://ww1.microchip.com/downloads/en/devicedoc/11195c.pdf

According to the timing diagram: enter image description here

It mentions that Data is always latched in on the rising edge of the SCK. Is that supposed to give me any hints about CPHA?

It also mentions that the Data is always clocked out of the SO pin after the falling edge of SCK. Since it mentions falling edge of the SCK, I understand that the CPHA for this device should be set to 1, is that correct?

2 What if I have 2 SPI devices connected to the same SPI bus. One device requires CPOL = 0, CPHA = 0 and the other device requires CPOL = 0 and CPHA = 1. Does that mean it will not be possible to communicate with both devices via single SPI bus?

microcontroller spi stm32
1 Answers

The timing diagram shows that this device requires SPI mode 0: CPOL=0 CPHA=0.

The way to read the diagram is that the clock idles low, so CPOL=0. The data is sampled (called "latched" above) on the rising edge. This is the first edge when starting low so CPHA=0 (the rising edge would be the second edge if starting high).

The comment about output data on the falling edge simply means that the device outputs the next data starting on the second edge of the preceding pulse, this way it is ready in time for the first edge of the next clock pulse.

For your second question, yes you can mix different clock modes (polarity, phase and speed) on the same bus, as long as you make all the changes when no device is selected, ie: when all chip-selects are high. You may want to even change the mode of the chip select pins momentarily to GPIO while you deconfigure and reconfigure the SPI peripheral (I'm never sure what alt-function pins will output while you are messing with the registers of a disabled peripheral).

Tom V0
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